Free Electronics and Devices MCQs with Answers

• A. Maximum voltage appears across transistor
• B. Maximum current flows
• C. Maximum voltage appears across load
• D. None of the aboveTransistors

Explanation: When the transistor is cut off, its collector current is nearly zero, so the voltage drop across the transistor reaches its maximum.

• A. 5 W
• B. 33 W
• C. 75 W
• D. 1 W

Explanation: The transistor's power rating must be at least equal to its maximum expected dissipation; with a zero-signal dissipation of 1 W, the…

• A. Push-pull amplifier
• B. Preamplifier
• C. Class A power amplifier
• D. None of the above

Explanation: The output stage must deliver relatively high power to the load, so it commonly uses a push-pull power amplifier.

• A. Provide easy handling
• B. Dissipate heat
• C. Facilitate connections
• D. None of the above

Explanation: Power transistors handle substantial current and power, so their larger physical area provides better heat dissipation through the case…

• A. A
• B. B
• C. C
• D. AB

Explanation: Class C operation conducts for less than half of the input cycle, producing strong harmonic distortion.

• A. OR gate
• B. AND gate
• C. NOT gate
• D. None of the above

Explanation: When both inputs of a NAND gate are tied together as A, its output is (A·A)' = A', which is the NOT function.

• A. NAND gate
• B. OR gate
• C. AND gate
• D. None of the aboveGet Study Guides

Explanation: A NAND gate is universal because combinations of NAND gates can implement NOT, AND, and OR functions, and therefore any Boolean circuit.

• A. A & B
• B. C & D
• C. A & D
• D. B & C

Explanation: Smaller FPGA logic modules require more modules and interconnections to implement the same function, increasing routing delay and…

• A. PLCC
• B. QFP
• C. PGA
• D. BGALearn Quantum Physics

Explanation: A BGA package uses an array of solder balls beneath the package, allowing many closely spaced connections in a small area.

• A. OR operation
• B. AND operation
• C. NOT operation
• D. None of the above

Explanation: A bar over a Boolean variable or expression denotes its complement, which is the NOT operation. For example, the bar over A represents A'.

• A. Input operation
• B. Tristate output operation
• C. Bi-directional I/O pin access
• D. All of the aboveCompare Home Electronics

Explanation: An FPGA input/output block can be configured for input, tristate output, or bidirectional operation.

• A. State Reduction
• B. State Minimization
• C. State Assignment
• D. State Evaluation

Explanation: State assignment is the process of assigning binary codes to the symbolic states of a sequential circuit.

• A. OR gates
• B. NOT gates
• C. NAND gates
• D. None of the above

Explanation: NAND is a universal gate, so combinations of NAND gates can implement NOT, AND, and OR functions and therefore any digital circuit.

• A. 0
• B. 1
• C. Either 0 & 1
• D. None of the aboveHire Civil Engineers

Explanation: A NOT gate complements its input, so an input of 1 produces an output of 0. An output of 1 occurs only when the input is 0.

• A. NOT gate
• B. OR gate
• C. AND gate
• D. None of the aboveCompare Local Schools

Explanation: A NAND gate is formed by connecting a NOT gate to the output of an AND gate. Thus, its output is the complement of the AND operation.

• A. Stop signal
• B. Invert input signal
• C. Act as a universal gate
• D. None of the aboveGet Study Guides

Explanation: A NOT gate reverses or inverts the input logic level: 0 becomes 1 and 1 becomes 0. It is not a universal gate, unlike NAND and NOR gates.

• A. AND gate
• B. NAND gate
• C. NOT gate
• D. None of the aboveLearn Quantum Physics

Explanation: A NOR gate is made by placing a NOT gate after an OR gate, so its output is the complement of the OR result.

• A. NOT gate
• B. OR gate
• C. AND gate
• D. None of the above

Explanation: An inverter performs logical complementation, which is exactly the function of a NOT gate.

• A. 19
• B. 12
• C. 27
• D. 21

Explanation: In 10101, the set bits represent 16, 4, and 1; their sum is 21. Therefore, the binary number converts to decimal as 16 + 4 + 1 = 21.

• A. 2TTL
• B. 5TTL
• C. 8TTL
• D. 10TTL

Explanation: The standard fan-out of a 7400-series TTL NAND gate is 10, meaning one output can drive up to ten standard TTL inputs.